The first four-bit data register 1 has four latch circuits 8, 9, 10 and 11 arranged in parallel, and each of the latch circuits 8, 9, 10 and 11 comprises two inverter circuits 25 and 26 coupled in series for memorizing a data bit and two n-channel type field effect transistors 27 and 28 one of which is coupled between the first data bus system 2 and the inverter circuit 12 and responsive to a latching signal S1 for taking the data bit therein and the other of which is coupled between the inverter circuits 13 and 12 and responsive to a retaining signal S2 for allowing the series combination of the inverter circuits 12 and 13 to retain the data bit. Input data bit groups are serially supplied from the first data bus system 2 to the first data register 1 and memorized thereinto.
The second data register 5 also has four latch circuits 12, 13, 14 and 15 each provided with two inverter circuits 16 and 17 and two n-channel type field effect transistor 18 and 19. Each of the latch circuits 12, 13, 14 and 15 is similar in circuit behavior to the latch circuit 8, so that a reference data bit group is supplied from the second data bus system 6 and latched thereinto in response to a latching signal S3 and a retaining signal S4. The comparator circuit 7 comprises four two-input exclusive-OR gates 20, 21, 22 and 23 each coupled to both data registers 1 and 5 and a four-input NOR gate 24 coupled to the exclusive-OR gates 20, 21, 22 and 23.
In operation, when the reference data bit group (0101) is supplied to the second data bus system 6, the latch circuits 12, 13, 14 and 15 are responsive to the latching signal S3 to take the reference data bit group thereinto and, then, to the retaining signal S4 to memorize the reference data bit group thereinto. After the reference data bit group is memorized into the second data register 5, input data bit groups are successively supplied to the first data bus system 2, and the first data register 1 is responsive to the latching signal S1 and, then, the retaining signal S2 for memorizing the data bit groups in succession. If the input data bit groups have respective bit strings shown in Table 1, the exclusive-OR gates to 23 and, accordingly, the NOR gate 24 produces the output signals which are also indicated in Table 1.
TABLE 1 __________________________________________________________________________ First data Second data EX-OR EX-OR EX-OR EX-OR NOR register 1 register 5 23 22 21 20 24 __________________________________________________________________________ 0 0000 0101 0 1 0 1 0 1 0001 0101 0 1 0 0 0 2 0010 0101 0 1 1 1 0 3 0011 0101 0 1 1 0 0 4 0100 0101 0 0 0 1 0 5 0101 0101 0 0 0 0 1 6 0110 0101 0 0 1 1 0 7 0111 0101 0 0 1 0 0 8 1000 0101 1 1 0 1 0 9 1001 0101 1 1 0 0 0 A 1010 0101 1 1 1 1 0 B 1011 0101 1 1 1 0 0 C 1100 0101 1 0 0 1 0 D 1101 0101 1 0 0 0 0 E 1110 0101 1 0 1 1 0 F 1111 0101 1 0 1 0 0 __________________________________________________________________________
Thus, the prior-art comparator unit is operative to detect the input data bit group identical in bit string with the reference data bit group. However, when the comparator unit forms part of a data processing system shown in FIG. 2 and serves as an address space discriminating circuit, a problem is encountered in circuit complexity. In detail, in the data processing system the comparator unit 31 is supplied with a reference address data bit group through the second bus system 6 and with an address data bit group through the first bus system 2 for the comparison. If the address space shown in FIG. 3 is provided to the data processing system, a central processing unit 32 needs to enter the wait state in at address locations 5 and D, because of a difference in operation speed between the central processing unit 32 and a memory unit 33 or an interface unit 34. For this reason, the central processing unit 32 provides the reference address data bit groups representative of the address location 5 and D to the comparator unit 31 through the second bus system 6, and the address data bits groups are successively latched into the comparator unit 31 for detecting the address locations 5 and D. FIG. 4 shows the discriminating operation for the address location 5. The reference address data bit group representative of the address location 5 is latched in the comparator unit 31 at time t1 and retained at time t2. If the address data bit group is indicative of the address locations 5 (at time t3) and D, the comparator unit 31 produces a detecting signal and causes a wait-state controller 35 to produce a wait control signal which is supplied to the central processing unit 32.
In this usage, the comparator unit 31 is expected to detect the two different address locations 5 and D, so that it is necessary to have two second data registers 41 and 42 for the address locations 5 and D, two comparator circuits 43 and 44 and a OR gate as shown in FIG. 5. Even if the first data resistor 46 is shared by the comparator circuits 43 and 44, the dualization makes the comparator unit 31 complicate.